The present invention, in some embodiments thereof, relates to a Dual Mode Logic (DML) family and, more particularly, but not exclusively, to a DML family with transistor sizing methodologies.
With advancements in technology and the expansion of mobile applications, power consumption has become a primary focus of attention in VLSI digital design. Recently, digital sub-threshold circuit design has become a very promising method for ultra-low power applications. Circuits, operating in the sub-threshold region, utilize a supply voltage (VDD) that comes close to or is even less than the threshold voltages of the transistors, so it allows significant reduction of both dynamic and static power. However, an aggressive scaling of supply voltage also results in performance degradation and a much higher sensitivity to process variations and temperature fluctuations.
The most common logic design family used for sub-threshold today is CMOS. Ultra low Voltage (ULV) operation originally introduced in 1972, first, originally used for low throughput applications like wrist watches, biomedical devices and sensors, offers low to moderate performance—up to 50 Mhz—while maintaining low-power dissipation. In 1999 CMOS sub-threshold design was introduced again.
The advantages offered by a conventional CMOS design methodology are well known and widely explored. They include: rail to rail logic levels, strong on and off states, and, various others. Until more recent processes, the CMOS methodology also featured very low static power consumption.
These advantages were also gained by sub-threshold designs. Low voltage operation of Static CMOS logic is quite straightforward, as its non-ratioed structure generally achieves robust operation However, in state of the art nano-scale processes in which the feature size is decreased beyond a hundred nanometers, the sub-threshold slope is increased, resulting in a decreased Ion/Ioff ratio. This prevents the designing of digital gates with large fan-ins, because retaining a logical level may not always be possible when contending with strong opposite leakage, especially under process variations and device mismatch.
Dynamic Logic, such as Domino logic, has been used since the 1970's for high performance applications. Some of the advantages of basic dynamic logic over CMOS logic are reduced area, high performance and, in some cases, reduced power consumption. However, dynamic logic also presents a number of significant drawbacks, such as bulky design, charge sharing, high dynamic power consumption and glitches susceptibility, which intensify with process and voltage scaling. In the past there were several attempts to use dynamic logic in sub-threshold to improve the speed, but because of high sensitivity to process variations in nano-scale technologies, these attempts did not gain momentum. Moreover, recently, the aforementioned problems have even reduced the utilization of super-threshold dynamic logic in recent processes.
Low voltage logic is not widely used as yet, mainly due to significant degradation in performance. Domino low voltage logic was introduced as a possible solution; however, it has not been in use due to high sensitivity to process variations. Moreover, with process scaling, dynamic logic is being abandoned even in the super-threshold regime, due to very low yield and logic failures. The same issues arise at standard operating voltage levels as well. Static logic is power-efficient but slow, whereas dynamic logic faster but at the cost of higher power consumption.
In the last years, there has been a spread of new non-traditional computing platforms with high processing capabilities and mobility requirements. The applications based on these computing platforms are characterized by a non-constant resource usage and time varying workload. Various solutions, such as Dynamic Voltage Scaling, threshold balancing and the recently introduced third generation of SmartReflex have proposed to better fit the requirements of these platforms.
Transistor sizing is a significant element of logic circuit design. Logical effort analysis is sometimes utilized to optimize transistor sizing for a minimal circuit delay.
None of the currently known circuit topologies provides the benefits of both low power operation and minimal circuit delay.
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